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| encore? v low voltage microcontroller cy7c60445, cy7c6045x preliminary cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12395 rev. *f revised march 19, 2008 features powerful harvard architecture processor ? m8c processor speeds running up to 24 mhz ? low power at high processing speeds ? interrupt controller ? 1.71v to 3.6v operating voltage ? temperature range: 0c to 70c flexible on-chip memory ? up to 32k flash program storage 50,000 erase/write cycles ? up to 2048 bytes sram data storage ? flexible protection modes ? in-system serial programming (issp) complete development tools ? free development tool (psoc designer?) ? full featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? crystal-less oscillator with support for an external crystal or resonator ? internal 5.0% 6, 12, or 24 mhz main oscillator ? internal low speed oscillator at 32 khz for watchdog and sleep.the frequency range is 19?50 khz with a 32 khz typical value programmable pin configurations ? 25 ma sink current on all gpio ? pull up, high z, open drain, cmos drive modes on all gpio ? configurable inputs on all gpio ? low dropout voltage regulator for port1 pins. programmable to output 3.0, 2.5, or 1.8v at the i/o pins ? selectable, regulated digital io on port 1 ? configurable input threshold for port 1 ? 3.0v, 20 ma total port 1 source current ? hot-swappable ? 5 ma strong drive mode on ports 0 and 1 additional system resources ? configurable communication speeds ? i 2 c? slave ? selectable to 50 khz, 100 khz, or 400 khz ? implementation requires no clock stretching ? implementation during sleep modes with less than 100 ma ? hardware address detection ? spi master and spi slave ? configurable between 46.9 khz and 3 mhz ? three 16-bit timers ? 10-bit adc for monitoring battery voltage or other signals ? watchdog and sleep timers ? integrated supervisory circuit system bus 6/12/24 mhz internal main oscillator cpu core (m8c) srom flash 32k system resources i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog port 3 port 2 prog. ldo sram 2048 bytes interrupt controller encore v low voltage core 3 16-bit timers port 4 encore v lv block diagram [+] feedback
preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 2 of 27 functional overview the encore v lv family of devices are designed to replace multiple traditional low voltag e microcontroller system compo- nents with one, low cost single chip programmable component. communication peripherals (i2c /spi), a fast cpu, flash program memory, sram data memo ry, and configurable io are included in a range of convenient pinouts. the architecture for this device family, as illustrated in encore v lv block diagram, is comprised of two main areas: the cpu core and the system resources. depending on the encore v lv package, up to 36 general purpose io (gpio) are also included. enhancements over the cypress? legacy low voltage microcon- trollers include faster cpu at lower voltage operation, lower current consumption, twice t he ram and flash, hot-swapable ios, i2c hardware address recognition, new very low current sleep mode, and new package options. the encore v lv core the encore v lv core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-mips, 8-bit harvard architecture microprocessor. system resources provide additional capability, such as a configurable i2c slave and spi master-slave communication interface and various system re sets supported by the m8c. additional system resources system resources, some of which have been previously listed, provide additional ca pability useful to complete systems. additional resources include low voltage detection and power on reset. brief statements describ ing the merits of each system resource are presented below. 10-bit on-chip adc shared between system performance manager (used to calculate para meters based on temperature for flash write operations) and the user. the i2c slave and spi master-slave module provides 50, 100, or 400 khz communication over two wires. spi communication over 3 or 4 wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). in i2c slave mode the hardware address recognition feature reduces the already low power c onsumption by eliminating the need for cpu intervention until a packet addressed to the target device has been received. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. the 5v maximum input, 1.8, 2.5, or 3v selectable output, low dropout regulator (ldo ) provides regulation for ios. a register controlled bypass mode allows the user to disable the ldo. standard cypress psoc ide tools are available for debugging the encore v lv family of parts. getting started the quickest path to understanding the encore v lv silicon is by reading this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an overview of the encore v lv integrated circuit and presents specific pin, register, and electrical specifications. for up to date ordering, packaging, and electrical specification information, refer the latest encore v lv device data sheet at http://www.cypress.com . development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com , click the online store shopping cart icon at the bottom of the web page, and click on usb (universal serial bus) to view a current list of available items. technical training free encore v lv microcontrollers technical training is available for beginners and is taught by a marketing or application engineer over the phone. low vo ltage microcontroller training classes cover designing, debugging, analog, and application specific classes covering topics such as psoc, usb and the lin bus. go to http://www.cypress.com , click on design support located on the left side of the web page, and select technical training for more details. consultants certified cypress consultants offer everything from technical assistance to completed microcon troller designs. to contact or become a cypress psoc/usb/microcontroller consultant go to http://www.cypress.com , click on design support located on the left side of the web page, and select cypros consultants. technical support cypress application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.c om/support/login.cfm . [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 3 of 27 development tools psoc designer is a microsoft ? windows based, integrated development environment for the programmable system-on-chip (psoc) devic es. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (reference the psoc designer functional flow diagram below.) psoc designer helps the customer to select an operating config- uration for the microcontroller, write application code that uses its resources, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high level c language compiler developed specifically for the devices in the family. figure 1. psoc designer subsystems psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the encore v lv device blocks. examples of user modules are timers, 10-bit adc, and spi/i2c. the device editor also supports easy development of multiple configurations and dynamic reco nfiguration. dynamic reconfigu- ration allows changing configurations at run time. psoc designer sets up power on initialization tables for selected encore v lv block configurations and creates source code for an application framework. the fr amework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of encore v lv block configurations at run time. psoc designer prints out a configuration sheet for a given project configurati on for use during application programming in conjunction with the device data sheet. when the framework is generated, the user can add application specific code to flesh out the framework. it is also possible to change the selected components and r egenerate the framework. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, compile, link, and build. assembler. the macro assembler allows merging of assembly code seamlessly with c code. the link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the encore v lv family of devices. even if you have never worked in c language before, the product allows you to create complete c programs for t he encore v lv family devices. the embedded, optimizing c compiler provides all the features of c tailored to the encore v lv architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing th e designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays online, co ntext sensitive help. designed for procedural and quick reference, each functional subsystem has its own context se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 4 of 27 hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is available for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with most cypress usb devices and all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the encore v lv in the target board and performs full speed (24 mhz) operation. designing with user modules to speed the development process, the psoc designer integrated development environm ent (ide) provides a feature where the resources of the part can be selected as user modules. for example, the timers, i2c, spi resources are available as user modules. us er modules make selecting and implementing peripheral devices simple and easy. each user module establishes t he basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are document ed in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specificatio ns. each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) to configure the hardware. pick and place the user modules required for your project. the tool automatically builds signal chains by connecting user modules to the default io pins or as required. at this stage, configur e the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate applicat ion? step. this causes psoc designer to generate source code that automatically configures the device to your spec ification and provides the high level user module api functions. figure 2. user module and source code development flows the next step is to write your main program, and any sub routines using psoc designer?s applicati on editor subsystem. the appli- cation editor includes a project manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a professional strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as necessary. project level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is corre ct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger downloads the hex image to the in -circuit emulator (ice) where it runs at full speed. debugger ca pabilities rival those of systems costing many times more. in addition to traditional single step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector user module selection generate application build all event & breakpoint manager build manager source code generator [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 5 of 27 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 6 on page 14 lists all the abbreviations used to measure the encore v lv devices. numeric naming hexidecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. acronym description api application programming interface cpu central processing unit gpio general purpose io gui graphical user interface ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output lsb least significant bit lvd low voltage detect msb most significant bit por power on reset ppor precision power on reset psoc? programmable system-on-chip? slimo slow imo sram static random access memory [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 6 of 27 pin configuration 32-pin part pinout figure 3. cy7c60445 32-pin encore v lv device table 1. 32-pin part pinout (qfn) pin no. type name description 1 ioh p0[1] digital io 2 io p2[7] digital io 3 io p2[5] digital io, crystal out (xout) 4 io p2[3] digital io, crystal in (xin) 5 io p2[1] digital io 6 io p3[3] digital io 7 io p3[1] digital io 8 iohr p1[7] digital io, i2c scl, spi ss 9 iohr p1[5] digital io, i2c sda, spi miso 10 iohr p1[3] digital io, spi clk 11 iohr p1[1] (1, 2) digital io, issp clk, i2c scl, spi mosi 12 power vss ground connection 13 iohr p1[0] (1, 2) digital io, issp data, i2c sda, spi clk note 1. during power up or reset event, device p1[0] and p1[1] may dist urb the i2c bus. use alternate pi ns if issues are encountered. 2. these are the in-system serial programming (issp) pins, that are not high z at power on reset (por). p0[1] p2[7] p2[5] p2[3] p2[1] p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3] p0[7] vdd p0[6] p0[4] p0[2] p3[1] p1[7] p0[0] p2[6] p3[0] xres p1[5] p1[3] p1[1] vss p1[0] p1[2] p1[4] p1[6] p2[4] p2[2] p2[0] p3[2] p0[5] [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 7 of 27 14 iohr p1[2] digital io 15 iohr p1[4] digital io, optional external clock input (extclk) 16 iohr p1[6] digital io 17 reset input xres active high external reset with internal pull down 18 io p3[0] digital io 19 io p3[2] digital io 20 io p2[0] digital io 21 io p2[2] digital io 22 io p2[4] digital io 23 io p2[6] digital io 24 ioh p0[0] digital io 25 ioh p0[2] digital io 26 ioh p0[4] digital io 27 ioh p0[6] digital io 28 power vdd supply voltage 29 ioh p0[7] digital io 30 ioh p0[5] digital io 31 ioh p0[3] digital io 32 power vss ground connection cp power vss center pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output. table 1. 32-pin part pinout (qfn) (continued) pin no. type name description [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 8 of 27 48-pin part pinout figure 4. cy7c60455/cy7c60456 48-pin encore v lv device table 2. 48-pin part pinout (qfn) pin no. type name description 1nc nc no connection 2 io p2[7] digital i/o 3 io p2[5] digital i/o, crystal out (xout) 4 io p2[3] digital i/o, crystal in (xin) 5 io p2[1] digital i/o 6 io p4[3] digital i/o 7 io p4[1] digital i/o 8 io p3[7] digital i/o 9 io p3[5] digital i/o 10 io p3[3] digital i/o 11 io p3[1] digital i/o 12 iohr p1[7] digital i/o, i2c scl, spi ss 13 iohr p1[5] digital i/o, i2c sda, spi miso 14 nc nc no connection 15 nc nc no connection qfn (top view) p0[1] vss p0[3] p0[5] p0[7] vdd p0[6] 10 11 12 p2[7] p2[5] p2[3] p2[1] p4[3] p4[1] p3[7] p3[5] p3[3] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p0[2] p0[0] p2[6] p2[4] p2[2] p2[0] p3[2] p3[0] xres p1[6] p0[4] 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 nc nc p1[3] p1[1] vss nc nc vdd p1[0] p1[2] p1[4] nc p3[1] p1[7] p1[5] p3[4] p3[6] p4[0] p4[2] nc nc [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 9 of 27 16 iohr p1[3] digital i/o, spi clk 17 iohr p1[1] (1, 2) digital i/o, issp clk, i2c scl, spi mosi 18 power vss supply ground 19 nc nc no connection 20 nc nc no connection 21 power vdd supply voltage 22 iohr p1[0] (1, 2) digital i/o, issp data, i2c sda, spi clk 23 iohr p1[2] digital i/o 24 iohr p1[4] digital i/o, optional external clock input (extclk) 25 iohr p1[6] digital i/o 26 xres ext reset active high external reset with internal pull down 27 io p3[0] digital i/o 28 io p3[2] digital i/o 29 io p3[4] digital i/o 30 io p3[6] digital i/o 31 io p4[0] digital i/o 32 io p4[2] digital i/o 33 io p2[0] digital i/o 34 io p2[2] digital i/o 35 io p2[4] digital i/o 36 io p2[6] digital i/o 37 ioh p0[0] digital i/o 38 ioh p0[2] digital i/o 39 ioh p0[4] digital i/o 40 ioh p0[6] digital i/o 41 power vdd supply voltage 42 nc nc no connection 43 nc nc no connection 44 ioh p0[7] digital i/o 45 ioh p0[5] digital i/o 46 ioh p0[3] digital i/o 47 power vss supply ground 48 ioh p0[1] digital i/o cp power vss center pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output table 2. 48-pin part pinout (qfn) (continued) pin no. type name description [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 10 of 27 register reference the section discusses the register s of the encore v lv device. it lists all the registers in mapping tables, in address order. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the encore v lv device has a total register address space of 512 bytes. the register space is also referred to as io space and is broken into two parts: bank 0 (user space) and bank 1 (config- uration space). the xio bit in the flag register (cpu_f) deter- mines which bank the user is currently in. when the xio bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. table 3. register conventions convention description r read register or bits w write register or bits o only a read/write register or bits l logical register or bits c clearable register or bits # access is bit specific table 4. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 80 c0 prt0ie 01 rw 41 81 c1 02 42 82 c2 03 43 83 c3 prt1dr 04 rw 44 84 c4 prt1ie 05 rw 45 85 c5 06 46 86 c6 07 47 87 c7 prt2dr 08 rw 48 88 i2c_xcfg c8 rw prt2ie 09 rw 49 89 i2c_xstat c9 r 0a 4a 8a i2c_addr ca rw 0b 4b 8b i2c_bp cb r prt3dr 0c rw 4c 8c i2c_cp cc r prt3ie 0d rw 4d 8d cpu_bp cd rw 0e 4e 8e cpu_cp ce r 0f 4f 8f i2c_buf cf rw prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 d9 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk2 de rw 1f 5f 9f int_msk1 df rw 20 60 a0 int_msk0 e0 rw 21 61 a1 int_sw_en e1 rw 22 62 a2 int_vc e2 rc 23 63 a3 res_wdt e3 w 24 64 a4 int_msk3 e4 rw gray fields are reserved and should not be acce ssed. # access is bit specific. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 11 of 27 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 e8 spi_txr 29 w 69 a9 e9 spi_rxr 2a r 6a aa ea spi_cr 2b # 6b ab eb 2c 6c ac ec 2d 6d ad ed 2e 6e ae ee 2f 6f af ef 30 70 pt0_cfg b0 rw f0 31 71 pt0_data1 b1 rw f1 32 72 pt0_data0 b2 rw f2 33 73 pt1_cfg b3 rw f3 34 74 pt1_data1 b4 rw f4 35 75 pt1_data0 b5 rw f5 36 76 pt2_cfg b6 rw f6 37 77 pt2_data1 b7 rw cpu_f f7 rl 38 78 pt2_data0 b8 rw f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # table 4. register map bank 0 table: user space (continued) name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access gray fields are reserved and should not be acce ssed. # access is bit specific. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 12 of 27 table 5. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 02 42 82 c2 03 43 83 c3 prt1dm0 04 rw 44 84 c4 prt1dm1 05 rw 45 85 c5 06 46 86 c6 07 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 0a 4a 8a ca 0b 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf prt4dm0 10 rw 50 90 d0 prt4dm1 11 rw 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 d8 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c io_cfg dc rw 1d 5d 9d out_p1 dd rw 1e 5e 9e de 1f 5f 9f df 20 60 a0 osc_cr0 e0 rw 21 61 a1 eco_cfg e1 # 22 62 a2 osc_cr2 e2 rw 23 63 a3 vlt_cr e3 rw 24 64 a4 vlt_cmp e4 r 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 imo_tr e8 w spi_cfg 29 rw 69 a9 ilo_tr e9 w 2a 6a aa ea 2b 6b ab slp_cfg eb rw 2c tmp_dr0 6c rw ac slp_cfg2 ec rw 2d tmp_dr1 6d rw ad slp_cfg3 ed rw 2e tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 b0 f0 31 71 b1 f1 32 72 b2 f2 33 73 b3 f3 34 74 b4 f4 35 75 b5 f5 36 76 b6 f6 37 77 b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa gray fields are reserved and should not be ac cessed. # access is bit specific. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 13 of 27 3b 7b bb fb 3c 7c bc fc 3d 7d bd fd 3e 7e be fe 3f 7f bf ff table 5. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access gray fields are reserved and should not be ac cessed. # access is bit specific. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 14 of 27 electrical specifications this section presents the dc and ac electric al specifications of the encore v lv dev ices. for the most up to date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com. figure 5. voltage versus cpu frequency figure 6. imo frequency trim options the following table lists the units of me asure that are used in this chapter. 3.6v 750 khz 24 mhz cpu frequency vdd voltage 1.71v 3 mhz v a l i d o p e r a t i n g r e g i o n 3.6v 750 khz 6 mhz 24 mhz imo frequency vdd voltage 3 mhz 1.71v slimo mode = 01 12 mhz slimo mode = 00 slimo mode = 10 table 6. units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k kilohm w ohm mhz megahertz pa picoampere m megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts s sigma: one standard deviation vrms microvolts root-mean-square v volts [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 15 of 27 electrical characteristics absolute maximum ratings storage temperature (t stg ) (3) ............................................. ...................................................... -55 o c to 125 o c (typical +25 o c) supply voltage relative to vss (v dd) .............. .............. ........ ........ .............. ........... ........... ........... .......................... -0.5v to +4.0v dc input voltage (v io )........................................................... ................................................................. vs s - 0.5v to vdd + 0.5v dc voltage applied to tri-state (v ioz )................................... ................................................................. vss - 0.5v to vdd + 0.5v maximum current into any port pin (i mio )............................. ............................................................................. -25ma to +50ma electro static discharge voltage (esd) (4) .............. .............. .. .............. .............. .............. .............. .............. .............. ........ 2000v latch-up current (lu) (5) ....................................................... ........................................................................ ..................... 200ma operating conditions ambient temperature (t a ) ..................................................... ......................................................................... ............0 o c to 70 o c operational die temperature (t j ) (6) ...................................... .....................................................................................0 o c to 85 o c dc electrical characteristics dc chip level specifications ta b l e 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. notes 3. higher storage temperatures reduce data retention time. recommended storage temperature is +25c 25c. extended duration st orage temperatures above 85c degrade reliability. 4. human body model esd. 5. per jesd78 standard. 6. the temperature rise from ambient to junction is pack age specific. see package diagram on page 24 for thermal impedances. the user must limit the power consumption to comply with this requirement. table 7. dc chip level specifications parameter description conditions min typ max units vdd supply voltage see table titled dc por and lvd specifications on page 19. 1.71 ? 3.6 v i dd24 supply current, imo = 24 mhz conditions are vdd = 3.0v, t a = 25 o c, cpu = 24 mhz no i2c/spi ? ? 3.1 ma i dd12 supply current, imo = 12 mhz conditions are vdd = 3.0v, t a = 25 o c, cpu = 12 mhz no i2c/spi ? ? 2.0 ma i dd6 supply current, imo = 6 mhz conditions are vdd = 3.0v, t a = 25 o c, cpu = 6 mhz no i2c/spi ? ? 1.5 ma i sb0 deep sleep current vdd = 3.0v, t a = 25 o c, io regulator turned off ? 0.1 ? a i sb1 standby current with por, lvd and sleep timer vdd = 3.0v, t a = 25 o c, io regulator turned off ? ? 1.5 a [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 16 of 27 dc general purpose io specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temper ature ranges: 1. 71v to 3.6v a nd 0 c t a 70 c. typical parameters apply to 3.3v at 25 c. these are for design guidance only. table 8. 3.0v to 3.6v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 1 ma, maximum of 20 ma source current in all ios vdd - 0.9 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 5 ma, maximum of 20 ma source current in all ios vdd - 0.9 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh < 10 a, vdd > 3.1v, maximum of 4 ios all sourcing 5 ma 2.85 3.00 3.15 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all ios 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all ios 2.35 2.50 2.65 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5v out ioh = 2 ma, vdd > 2.7v, maximum of 20 ma source current in all ios 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all ios 1.60 1.80 2.00 v v oh10 high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.7v, maximum of 20 ma source current in all ios 1.20 ? ? v v ol low output voltage iol = 25 ma, vdd > 3.3v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 1 - na c in capacitive load on pins as input package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf c out capacitive load on pins as output package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 17 of 27 table 9. 2.4v to 3.0v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.2 ma, maximum of 10 ma source current in all ios vdd - 0.4 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.4v, maximum of 20 ma source current in all ios. 1.50 1.80 2.00 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.4v, maximum of 20 ma source current in all ios 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? 0.72 v v ih input high voltage 2.0 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c in capacitive load on pins as input package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf c out capacitive load on pins as output package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 18 of 27 table 10. 1.71v to 2.4v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh = 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.5 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 100 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v ol low output voltage iol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.4v v il input low voltage ? ? 0.3 x vdd v v ih input high voltage 0.65 x vdd ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c in capacitive load on pins as input package and pin dependent. te m p = 2 5 o c 0.5 5 pf c out capacitive load on pins as output package and pin dependent te m p = 2 5 o c 0.5 5 pf [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 19 of 27 dc por and lvd specifications ta b l e 11 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. dc programming specifications ta b l e 1 2 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 11. dc por and lvd specifications symbol description min typ max units v ppor0 v ppor1 v ppor2 v ppor3 vdd value for ppor trip (7) porlev[1:0] = 00b, hpor = 0 porlev[1:0] = 00b, hpor = 1 porlev[1:0] = 01b, hpor = 1 porlev[1:0] = 10b, hpor = 1 1.61 1.66 2.36 2.60 2.82 1.71 2.40 2.65 2.95 v v v v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 vdd value for lvd trip vm[2:0] = 000b (8) vm[2:0] = 001b (9) vm[2:0] = 010b (10) vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b (11) 2.40 2.64 2.85 2.95 3.06 ? ? 2.45 2.71 2.92 3.02 3.13 1.9 1.8 2.51 2.78 2.99 3.09 3.20 ? ? v v v v table 12. dc programming specifications symbol description min typ max units vdd iwrite supply voltage for flash write operations 1.71 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? v il v v ihp input high voltage during programming or verify v ih ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify (12) ? ? 0.2 ma i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify (13) ? ? 1.5 ma v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash write endurance (14) 50,000 ? ? cycles flash dr flash data retention (15) 10 20 ? years notes 7. vdd must be greater than or equal to 1.71v during startup, reset from the xres pin, or reset from watchdog. 8. always greater than 50 mv above v ppor1 for falling supply. 9. always greater than 50 mv above v ppor2 for falling supply. 10. always greater than 50 mv above v ppor3 for falling supply. 11. always greater than 50 mv above v ppor0 voltage for falling supply. 12. driving internal pull down resistor. 13. driving internal pull down resistor. 14. erase/write cycles per block. 15. following maximum flash write cycles. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 20 of 27 ac electrical characteristics ac chip level specifications ta b l e 1 3 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 13. ac chip level specifications symbol description min typ max units f max maximum operating frequency (16) 24 ? ? mhz f cpu maximum processing frequency (17) 24 ? ? mhz f 32k1 internal low speed oscillator frequency 30.4 32 33.6 khz f imo24 internal main oscillator stability for 24 mhz 5% (18) 22.8 24 25.2 mhz f imo12 internal main oscillator stability for 12 mhz (19) 11.4 12 12.6 mhz f imo6 internal main oscillator stability for 6 mhz (20) 5.7 6.0 6.3 mhz dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s notes 16. digital clocking functions. 17. cpu speed. 18. trimmed using factory trim values. 19. trimmed using factory trim values. 20. trimmed using factory trim values. [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 21 of 27 ac general purpose io specifications ta b l e 1 4 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. table 14. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode, port 0, 1 0 0 0 ? ? ? 3 mhz for 1.71v preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 23 of 27 ac spi specifications ta b l e 1 7 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. ac i 2 c specifications ta b l e 1 8 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. figure 8. definition for timing for fast/standard mode on the i 2 c bus table 17. ac spi specifications symbol description min typ max units f spim maximum input clock frequency selection, master (21) ? ? 8.2 mhz f spis maximum input clock frequency selection, slave ? ? 4.1 mhz t ss width of ss_ negated between transmissions 50 ? ? ns notes 21. output clock frequency is half of input clock rate. 22. a fast mode i2c bus device can be used in a st andard mode i2c bus system, but the requirement t su;dat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal . if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard mode i2c bus specification) before the scl line is released. table 18. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 (22) ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a st op and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter ? ?050ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 24 of 27 package diagram this chapter illustrates the packaging specifications for the enco re v lv device, along with the thermal impedances for each pa ckage. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the encore v lv emulation tools and their dimensions, refer to the development kit . packaging dimensions figure 9. 32-lead (5x5 x 0.6 mm) qfn 001-06352 *b [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 25 of 27 figure 10. 48-lead (7x7 x 1mm) qfn 001-13191 ** [+] feedback preliminary cy7c60445, cy7c6045x document number: 001-12395 rev. *f page 26 of 27 thermal impedances solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. ordering information table 19. thermal impedances per package package typical ja * 32 qfn** 14.5 o c/w 48 qfn** 28 o c/w * t j = t a + power x ja ** to achieve the thermal impedance specified for the ** package, solder the center thermal pad to the pcb ground plane. table 20. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 32 qfn 240 o c 260 o c 48 qfn 240 o c 260 o c *higher temperatures may be required based on the solder melt ing point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. ordering code package information flash sram no. of gpios target applications cy7c60445-32lqxc 32-lead qfn (5x5x0.6mm) 16k 1k 28 feature-rich wireless mouse cy7c60445-32lqxct 32-lead qfn - (tape and reel) (5x5x0.6mm) 16k 1k 28 feature-rich wireless mouse cy7c60455-48ltxc 48-lead qfn (7x7x1mm) 16k 1k 36 mid-tier wireless keyboard cy7c60455-48ltxct 48-lead qfn - (tape and reel) (7x7x1mm) 16k 1k 36 mid-tier wireless keyboard cy7c60456-48ltxc 48-lead qfn (7x7x1mm) 32k 2k 36 feature-rich wireless keyboard CY7C60456-48LTXCT 48-lead qfn - (tape and reel) (7x7x1mm) 32k 2k 36 feature-rich wireless keyboard [+] feedback document number: 001-12395 rev. *f revised march 19, 2008 page 27 of 27 all products and company names mentioned in this document may be the trademarks of their respective holders. preliminary cy7c60445, cy7c6045x ? cypress semiconductor corporation, 2006-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy7c60445, cy7c6045x, encore? v low voltage microcontroller document number: 001-12395 rev. ecn. issue date orig. of change description of change ** 626516 see ecn tyj new data sheet *a 735721 see ecn tyj/ari added new block diagram, replaced tbds, corrected values, updated pinout information, changed part number to reflect new specifications. *b 1120504 see ecn ari corrected the description to pin 29 on table 1, the typ/max values for i sb0 on the dc chip-level specifications, and the min voltage value for vdd iwrite in the dc programming specifications table. corrected flash write endurance minimum value in the dc programming speci- fications table. corrected the flash erase time max va lue and the flash block write time max value in the ac programming specifications table. implemented new latest template. *c 1225864 see ecn aesa/ari corrected the description to pin 13, 29 on table 1 and 22,44 on table 2. added sections register reference, register conventions and register mapping tables. corrected max values on the dc chip-level specifications table. *d 1446763 see ecn aesa changed t eraseb parameter, max value to 18ms in table 13, ac programming specification. *e 1639963 see ecn aesa post to www.cypress.com *f 2138889 see ecn tyj/pyrs updated ordering code table: - ordering code changed for 32-qfn package: from -32lkxc to -32ltxc - added a new package type ? ?ltxc? for 48-qfn - included tape and reel ordering code for 32-qfn and 48-qfn packages changed active current values at 24, 12 an d 6mhz in table ?dc chip-level speci- fications? - idd24: 2.15 to 3.1ma - idd12: 1.45 to 2.0ma - idd6: 1.1 to 1.5ma added information on using p1[0] and p1[1 ] as the i2c interface during por or reset events [+] feedback |
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